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Journal for Studies in Management and Planning

Available at http://edupediapublications.org/journals/index.php/JSMaP/

e-ISSN: 2395-0463

Volume 02 Issue 11

November 2016

Available online:http://edupediapublications.org/journals/index.php/JSMaP/ P a g e | 153

Coding Script to Avoid Data Corruption To Protect

Memories

1Kukkala Venkatesh, 2Mr.P.V.Vara Prasad Rao

1

PG Scholar, Department of ECE, SLC's Institute of Engineering and Technology, Piglipur Village, Hayathnagar

Mandal, Near Ramoji Film City, Ranga Reddy District, Hyderabad, Telangana

2Assosciate Professor, Department of ECE, SLC's Institute of Engineering and Technology, Piglipur Village,

Hayathnagar Mandal, Near Ramoji Film City, Ranga Reddy District, Hyderabad, Telangana

ABSTRACT:

The primary challenge is the fact that individual’s codes should minimize the delay and area

penalty. One of the codes which have been considered for memory protection is Reed-Solomon

(RS) codes. This limits using ECCs in high-speed recollections. It has brought to using simple

codes for example single error correction double error recognition (SEC-DED) codes. However,

as technology scales multiple cell upsets (MCUs) be common and limit using SEC-DED codes

unless of course they're coupled with interleaving. To prevent data corruption, error correction

codes (ECCs) are broadly accustomed to safeguard recollections. ECCs introduce a delay penalty

in being able to access the information as encoding or deciphering needs to be carried out. An

identical issue happens in some kinds of recollections like DRAM which are typically arranged

in modules made up of several products. In individual’s modules, the security against a tool

failure instead of isolated bit errors can also be desirable. In individual’s cases, one option is by

using more complex ECCs that may correct multiple bit errors. These codes derive from non- binary symbols and for that reason can correct multiple bit errors. Within this paper, single

symbol error correction codes according to Reed-Solomon codes that may be implemented with

low delay are suggested and evaluated. The outcomes show that they'll be implemented having a

substantially lower delay than traditional single error correction RS codes.

Keywords: Error correction codes, reed-solomon codes, DRAM memorymodule, soft errors.

I. INTRODUCTION

ECCs then adds additional parity check bits

to every memory word so that errors could

be detected and remedied. These extra bits

lessen the effective capacity from the

memory. Errors could be caused for instance

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Journal for Studies in Management and Planning

Available at http://edupediapublications.org/journals/index.php/JSMaP/

e-ISSN: 2395-0463

Volume 02 Issue 11

November 2016

Available online:http://edupediapublications.org/journals/index.php/JSMaP/ P a g e | 154

by radiation caused soft errors affecting a

number of memory cells and alter their

values. Data corruption brought on by errors

is really a serious problem in recollections

other kinds of failures cause permanent

damage so that the unit no more provides

correct data. To make sure that information

is not corrupted when failures occur, error

correction codes (ECCs) are broadly utilized

in recollections. Other overheads created by

the ECC would be the encoding and

deciphering circuitry. This circuitry comes

with an impact also around the delay

because the data needs to be encoded when

writing in to the memory and decoded when

studying from this. When multiple errors

affect cells which are physically close, out

of the box the situation of radiation caused

multiple cell upsets (MCUs), SEC-DED

codes could be coupled with interleaving to

make sure that the errors affect only one bit

per logical word. Generally, the deciphering

is much more complex compared to

encoding and limits the rate from the ECC.

Typically single error correction double

error recognition (SEC-DED) codes are

utilized to safeguard recollections. These

codes possess a minimum Hamming

distance of 4 so that single bit errors could

be remedied while double errors are detected

and never miscorrected. SEC-DED codes

could be implemented having a relatively

low area and delay overhead and a few

optimizations happen to be suggested

recently. Multiple bit errors are a problem

when SEC-DED codes are utilized. That's

even the situation when a mistake causes the

malfunction of the device inside a memory

module. For the reason that situation, the

term is split in sub-blocks as well as an ECC

can be used for all of them [1]. Then your

sub-blocks are interleaved within the

products so that inside a device there's only

one small given sub-block. However, using

interleaving comes with an effect on the

memory design and may increase area and

power. For any memory module, using

interleaving increases the amount of parity

check bits needed, to supplement bits are

needed per each one of the sub-blocks.

Finally, when multiple errors come from

independent error occasions, more effective

ECCs are necessary to make sure the

correction of errors. A large quantity of

multiple bit ECCs happen to be suggested to

safeguard recollections. Included in this are

Bose-Chaudhuri-Hocquenghem (BCH),

Euclidean Geometry, Difference Set,

Orthogonal Latin Squares and Reed- Solomon codes. Reed Solomon (RS) codes

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Journal for Studies in Management and Planning

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e-ISSN: 2395-0463

Volume 02 Issue 11

November 2016

Available online:http://edupediapublications.org/journals/index.php/JSMaP/ P a g e | 155

possess a distinct feature when in

comparison using the other codes: they

aren't binary. They will use symbols from

the Galois Field so that each symbol is

symbolized by multiple bits. Therefore a

SEC RS code can correct multiple bit errors

as lengthy because they affect just one

symbol. This is extremely attractive for

memory modules as when the amount of bits

within the products match’s individuals

from the symbols within the RS code,

failures in a single device could be

remedied. Actually, because of this RS

codes are generally accustomed to safeguard

primary recollections in personal computers

for space programs, for example individuals

described [2]. Generally, the information

that forms an RS code wordis thought as

polynomial coefficients with values of the

Galois Field. The polynomial akin to a code

word is really a multiple of the specific

polynomial, known as generator polynomial

g(x). Interested visitors can make reference

to a textbook on error control codes for more

particulars. Within the situation of SEC RS

codes, the code word consists by appending

two check symbols to some data word of k

symbols. To define the SEC RS codes,

normally the matrix representation is

preferred, thus the symbols creating the code

word are vectors of Galois Field elements.

For binary codes, a code is determined

utilizing a matrix H, known as parity check

matrix. A code word is really a vector v. The

encoding procedure for an information

vector d is carried out beginning from the

generator matrix G, by computing Gd,

which helps to ensure that Hv. Because the

SEC RS code is generally separable, the G

matrix assumes the shape G, where Ik is

really an identity matrix and P is of

dimension k x 2. Just like other advanced

ECCs one problem for using RS codes in

recollections may be the delay created by

the deciphering. Within the situation of RS

codes, several arithmetic procedures within

the Galois Field are necessary to encode or

decode a block. This produces a much

bigger delay compared to traditional SEC- DED codes. To mitigate the outcome on

delay when utilizing advanced ECCs, one

choice is to do error recognition first and

just when errors are detected go to the

correction phase. As errors are rare, the

typical delay will bond with those of the

mistake free situation that is given when

needed to do error recognition only. This

really is reduced compared to time required

for correction. However, despite this

modification delay could be large because